1. Field of the Invention
This invention relates generally to frequency shift keying (FSK) modulation and demodulation techniques. More particularly, it relates to cost-effective binary frequency shift keying (BFSK) modulator and demodulator techniques which are capable of being implemented in the digital domain with relatively simple logic gate circuitry and are also capable of being extended easily and economically to support M-ary FSK techniques where multiple bits are transmitted simultaneously through the use of overloaded symbols from a set of frequencies larger than two (2).
2. Background of Related Art
In today's digitally-oriented, increasingly mobile, wireless world, modulators and demodulators provide a necessary radio frequency ("RF") link for systems such as cordless phones, wireless networks, etc.
Many digital encoding standards exist which allow larger amounts of data to be transmitted over such wireless RF links in shorter amounts of time. For instance, one well-known digital encoding technique is frequency shift keying (FSK).
In its simplest form, FSK provides two discrete RF frequencies which can be used to transmit two data states, i.e., a `1` bit or a `0` bit. This is known as binary FSK or BFSK. In advanced forms ("M-ary FSK"), FSK may employ multiple frequencies which are each uniquely mapped to represent more than one bit per symbol, allowing the simultaneous transmission of multiple bits of data in a single symbol interval ("symbol overloading").
For instance, using four different frequencies, two (2) bits per symbol may be encoded into and transmitted simultaneously with each symbol represented by one of the four unique frequencies.
In their simplest form, binary FSK modulation techniques would produce a square wave type signal, and the signal would consequently contain a relatively high level of side lobe spectrum energy. This side lobe spectrum energy (which could cause interference to adjacent channels) is typically suppressed either by baseband pulse shaping (most common), or bandpass filtering at IF.
Baseband pulse shaping is in essence a lowpass filtering of the baseband data pulses. Bandpass filtering filters the output of the modulator at an intermediate frequency stage where a fixed frequency bandpass filter with appropriate bandwidth and shape factor may be employed. Such filtering may be accomplished either in digital form or in analog form, depending on the exact implementation. Either form of side lobe suppression utilizes a significant amount of space in a circuit, and can be relatively expensive and complicated to manufacture.
In a consumer-oriented environment in particular, costs are to be minimized. One way to accomplish this is to reduce the area and power required to perform a particular function in an integrated circuit.
Reducing power consumption is also desirable, particularly in battery-powered portable equipment. In addition to reducing costs, reduced power can extend battery life or permit the use of a smaller battery for a given period of operation before it becomes necessary to re-charge the battery.
Baseband pulse shaping requires a significant amount of circuitry, either in the form of analog pulse shaping filters or in the circuitry required to generate a stepped digital approximation of the shaped pulse. The latter technique generally requires at least one, and often two, multi-bit precision Digital to Analog Converters ("DACs"), which consume significant integrated circuit area and power. Because of the costs associated with the various methods of baseband pulse shaping, elimination of the need for baseband pulse shaping would be desirable.
Bandpass filtering at an intermediate frequency can be essentially equivalent to baseband pulse shaping in terms of the suppression of undesired side lobe energy. The cost of such filtering is strongly dependent on the choice of IF frequency and the percentage bandwidth and selectivity required to adequately suppress the side lobe energy, but in many cases such filtering at IF can be less than the costs associated with baseband pulse shaping.
Side lobe energy levels are also strongly influenced by whether the FSK modulation technique results in continuous phase ("CPM") or non-continuous phase ("NCPM") modulation. CPM FSK results in side lobe levels which are approximately 27 dB below the peak level of the desired signal, whereas NCPM FSK results in side lobe levels which are only approximately 13 dB below the peak level of the desired signal. Thus, CPM FSK modulation techniques are desirable in that they inherently reduce side lobe energy levels, providing improved adjacent channel protection and reducing costs by easing filtering requirements to achieve a given level of adjacent channel protection.
NCPM FSK can be produced by modulating a conventional FM modulator or PLL with shaped baseband data pulses. Traditionally, NCPM techniques have been less costly, but offer poorer performance relative to DDS-based CPM FSK techniques.
Similarly, on the demodulator side, prior art FSK demodulation techniques fall into two general categories.
First, FSK signals can be non-coherently demodulated by a variety of well-known FM demodulation techniques such as the classical limiter/discriminator, Phase-Locked Loop ("PLL") demodulators, and the commonly used "quadrature detector" frequency discriminator employed in many FM radios, followed by a "slicer" (comparator) which compares the output level from the FM demodulator to a reference level to make the "1/0" symbol value decision.
Alternatively, techniques, such analog-to-digital (A/D) and digital-to-analog (D/A) based "I/Q" demodulation and integrate and dump matched filtering can give significantly better demodulator performance. However, the improved performance comes at the expense of circuit complexity, cost, and power consumption associated with the multi-bit analog to digital converters ("ADCs") and digital signal processing which have traditionally been required by prior art implementations of such techniques.
There is a need for improved FSK modulation and demodulation techniques which result in the simplification of the circuitry involved and reduce implementation costs and power consumption, while providing performance closely approaching the theoretical ideal.